module control(/*AUTOARG*/
   // Outputs
   ctrl_o_signals, ctrl_mem_o_valid,
   // Inputs
   clk, reset, ctrl_i_opcode, ctrl_i_funct
   );


input clk;
input reset;
input [5:0] ctrl_i_opcode;
input [5:0] ctrl_i_funct;
output [5:0] ctrl_o_signals;
output [3:0] ctrl_mem_o_valid;

reg [5:0] ctrl_o_signal_w;
reg [3:0] ctrl_mem_b_valid;
/*
bit 5 -> AluSrc
bit 4 -> AluOp1
bit 3 -> AluOp0
bit 2 -> mem_or_no
bit 1 -> mem_rd_wr#
bit 0 -> wb_or_no
*/


always @ (posedge clk or negedge reset)
begin
if(!reset)
	ctrl_o_signal_w <= 6'b000000;
else
	begin

	if (ctrl_i_opcode == 6'b000000)
		 begin
		 if(ctrl_i_funct == 6'b100000) //0x20
			ctrl_o_signal_w <= 6'b011001; //add ox19
		 else 
			if(ctrl_i_funct == 6'b100111)//0x27
				ctrl_o_signal_w <= 6'b010001; //nor 0x11
		 end
	else
		if(ctrl_i_opcode == 6'b001000) //0x08)
			ctrl_o_signal_w <= 6'b111001; //addi 0x39
		else
			if(ctrl_i_opcode == 6'b100011 || ctrl_i_opcode == 6'b100000)//0x23||0x20 
				ctrl_o_signal_w <= 6'b100111; //lw||lb 0x27
			else
				if(ctrl_i_opcode == 6'b101011 || ctrl_i_opcode  == 6'b101000)
					ctrl_o_signal_w <= 6'b100100; //sw||sb 0x24
				else
					if(ctrl_i_opcode == 6'b000100)
						ctrl_o_signal_w <= 6'b001000;//beq 0x08
					else
						ctrl_o_signal_w <= 6'b000000;
		
	if(ctrl_i_opcode == 6'b100000 || ctrl_i_opcode == 6'b101000)
		ctrl_mem_b_valid <= 4'b0001;
	else 
		if(ctrl_i_opcode == 6'b100011 || ctrl_i_opcode == 6'b101011)
			ctrl_mem_b_valid <= 4'b1111;
		else
			ctrl_mem_b_valid <= 4'b0000;

	end

end
assign ctrl_o_signals = ctrl_o_signal_w;
assign ctrl_mem_o_valid = ctrl_mem_b_valid;
endmodule

